This invention relates to non-volatile flash EEPROM (Electrically Erasable and Programmable Read Only Memory) cell arrays, primarily to the structure of memory cells and to processes of manufacturing memory arrays of them.
There are many commercially successful non-volatile memory products being used today, particularly in the form of small cards, which use a flash EEPROM array of cells having a “split-channel” between source and drain diffusions. The floating gate of the cell is positioned over one portion of the channel and the word line (also referred to as a control gate) is positioned over the other channel portion as well as the floating gate. This effectively forms a cell with two transistors in series, one (the memory transistor) with a combination of the amount of charge on the floating gate and the voltage on the word line controlling the amount of current that can flow through its portion of the channel, and the other (the select transistor) having the word line alone serving as its gate. The word line extends over a row of floating gates. Examples of such cells, their uses in memory systems and methods of manufacturing them are given in U.S. Pat. Nos. 5,070,032, 5,095,344, 5,315,541, 5,343,063, and 5,661,053, and in U.S. patent application Ser. No. 09/239,073, filed Jan. 27, 1999, now U.S. Pat. No. 6,281,075, which patents are incorporated herein by this reference.
A modification of this split-channel flash EEPROM cell adds a steering gate positioned between the floating gate and the word line. Each steering gate of an array extends over one column of floating gates, perpendicular to the word line. The effect is relieve the word line from having to perform two functions at the same time when reading or programming a selected cell. Those two functions are (1) to serve as a gate of a select transistor, thus requiring a proper voltage to turn the select transistor on and off, and (2) to drive the voltage of the floating gate to a desired level through an electric field (capacitive) coupling between the word line and the floating gate. It is often difficult to perform both of these functions in an optimum manner with a single voltage. With the addition of the steering gate, the word line need only perform function (1), while the added steering gate performs function (2). Further, such cells may operate with source side programming, having an advantage of lower programming voltages. The use of steering gates in a flash EEPROM array is described in U.S. Pat. Nos. 5,313,421, 5,712,180, and 6,222,762, which patents are incorporated herein by this reference.
Two techniques of removing charge from floating gates to erase memory cells are used in both of the two types of memory cell arrays described above. One is to erase to the substrate by applying appropriate voltages to the source, drain, substrate and other gate(s) that cause electrons to tunnel through a portion of a dielectric layer between the floating gate and the substrate. The other erase technique transfers electrons from the floating gate to another gate through a tunnel dielectric layer positioned between them. In the first type of cell described above, a third erase gate is provided for that purpose. In the second type of cell described above, which already has three gates because of the use of a steering gate, the floating gate is erased to the word line, without the necessity to add a fourth gate. Although this later technique adds back a second function to be performed by the word line, these functions are performed at different times, thus avoiding the necessity of making a compromise to accommodate the two functions.
It is continuously desired increase the amount of digital data that can be stored in a given area of a silicon substrate, in order to increase the storage capacity of a given size memory card and other types packages, or to both increase capacity and decrease size. One way to increase the storage density of data is to store more than one bit of data per memory cell. This is accomplished by dividing a window of a floating gate charge level voltage range into more than two states. The use of four such states allows each cell to store two bits of data, eight states stores four bits of data per cell, and so on. A multiple state flash EEPROM structure and operation is described in U.S. Pat. Nos. 5,043,940 and 5,172,338, which patents are incorporated herein by this reference.
Increased data density can also be achieved by reducing the physical size of the memory cells and/or of the overall array. Shrinking the size of integrated circuits is commonly performed for all types of circuits as processing techniques improve over time to permit implementing smaller feature sizes. But since there are limits of how far a given circuit layout can be shrunk by scaling through simple demagnification, efforts are also directed toward redesigning a feature to take up less area. Therefore, it is a primary object of the present invention to provide floating gate memory cell structures that permit increased data storage density by occupying less area as a result of at least one cell feature being redesigned.
It is a further object of the present invention to provide improved processing techniques for forming a flash EEPROM system utilizing such cells.